| Created (ET) |
Year |
DCN |
Rev |
Group |
Title |
Author (Affiliation) ▼ |
Uploaded (ET) |
Actions |
26-Jul-2017 ET |
2017 |
1183 |
2 |
TGax |
CR for CID 5772, 9476, 9480 |
Po-Kai Huang (Intel) |
26-Jul-2017 12:13:27 ET |
Download |
25-Jul-2017 ET |
2017 |
1183 |
1 |
TGax |
CR for CID 5772, 9476, 9480 |
Po-Kai Huang (Intel) |
25-Jul-2017 19:07:39 ET |
Download |
25-Jul-2017 ET |
2017 |
1183 |
0 |
TGax |
CR for CID 5772, 9476, 9480 |
Po-Kai Huang (Intel) |
25-Jul-2017 15:22:48 ET |
Download |
13-Jul-2017 ET |
2017 |
972 |
2 |
TGba |
Definition of WUR Mode |
Po-Kai Huang (Intel) |
13-Jul-2017 02:56:28 ET |
Download |
12-Jul-2017 ET |
2017 |
1077 |
1 |
TGax |
CR for 10.3.2.4 and 27.2.2 Part III |
Po-Kai Huang (Intel) |
12-Jul-2017 11:23:47 ET |
Download |
11-Jul-2017 ET |
2017 |
972 |
1 |
TGba |
Definition of WUR Mode |
Po-Kai Huang (Intel) |
11-Jul-2017 07:46:41 ET |
Download |
10-Jul-2017 ET |
2017 |
1077 |
0 |
TGax |
CR for 10.3.2.4 and 27.2.2 Part III |
Po-Kai Huang (Intel) |
12-Jul-2017 03:23:05 ET |
Download |
06-Jul-2017 ET |
2017 |
1008 |
0 |
TGba |
Vendor Specific WUR Frame |
Po-Kai Huang (Intel) |
09-Jul-2017 11:20:03 ET |
Download |
04-Jul-2017 ET |
2017 |
972 |
0 |
TGba |
Definition of WUR Mode |
Po-Kai Huang (Intel) |
09-Jul-2017 11:19:44 ET |
Download |
30-May-2017 ET |
2017 |
575 |
1 |
TGba |
Spec Framework |
Po-Kai Huang (Intel) |
30-May-2017 15:13:38 ET |
Download |
11-May-2017 ET |
2017 |
652 |
2 |
TGba |
Consideration of EDCA for WUR Signal |
Po-Kai Huang (Intel) |
11-May-2017 02:30:39 ET |
Download |
11-May-2017 ET |
2017 |
651 |
2 |
TGba |
Indication for WUR Duty Cycle |
Po-Kai Huang (Intel) |
11-May-2017 02:29:49 ET |
Download |
10-May-2017 ET |
2017 |
652 |
1 |
TGba |
Consideration of EDCA for WUR Signal |
Po-Kai Huang (Intel) |
10-May-2017 08:12:06 ET |
Download |
10-May-2017 ET |
2017 |
651 |
1 |
TGba |
Indication for WUR Duty Cycle |
Po-Kai Huang (Intel) |
10-May-2017 08:11:33 ET |
Download |
10-May-2017 ET |
2017 |
744 |
3 |
TGax |
CR for 10.3.2.4 and 27.2.2 Part II |
Po-Kai Huang (Intel) |
10-May-2017 07:49:41 ET |
Download |
10-May-2017 ET |
2017 |
744 |
2 |
TGax |
CR for 10.3.2.4 and 27.2.2 Part II |
Po-Kai Huang (Intel) |
10-May-2017 01:17:50 ET |
Download |
10-May-2017 ET |
2017 |
744 |
1 |
TGax |
CR for 10.3.2.4 and 27.2.2 Part II |
Po-Kai Huang (Intel) |
10-May-2017 00:22:53 ET |
Download |
08-May-2017 ET |
2017 |
707 |
1 |
TGax |
CR for CID 8555 |
Po-Kai Huang (Intel) |
08-May-2017 01:47:37 ET |
Download |
06-May-2017 ET |
2017 |
744 |
0 |
TGax |
CR for 10.3.2.4 and 27.2.2 Part II |
Po-Kai Huang (Intel) |
07-May-2017 11:04:07 ET |
Download |
03-May-2017 ET |
2017 |
707 |
0 |
TGax |
CR for CID 8555 |
Po-Kai Huang (Intel) |
03-May-2017 13:49:48 ET |
Download |
01-May-2017 ET |
2017 |
653 |
0 |
TGba |
Examples of Integrating WUR with Existing Power Save Protocol |
Po-Kai Huang (Intel) |
06-May-2017 23:33:01 ET |
Download |
01-May-2017 ET |
2017 |
652 |
0 |
TGba |
Consideration of EDCA for WUR Signal |
Po-Kai Huang (Intel) |
06-May-2017 23:29:49 ET |
Download |
01-May-2017 ET |
2017 |
651 |
0 |
TGba |
Indication for WUR Duty Cycle |
Po-Kai Huang (Intel) |
06-May-2017 23:24:55 ET |
Download |
05-Apr-2017 ET |
2017 |
575 |
0 |
TGba |
Spec Framework |
Po-Kai Huang (Intel) |
10-Apr-2017 20:25:40 ET |
Download |
17-Mar-2017 ET |
2017 |
343 |
3 |
TGba |
WUR Beacon |
Po-Kai Huang (Intel) |
17-Mar-2017 11:17:29 ET |
Download |
17-Mar-2017 ET |
2017 |
342 |
4 |
TGba |
WUR Negotiation and Acknowledgement Procedure Follow up |
Po-Kai Huang (Intel) |
17-Mar-2017 11:16:26 ET |
Download |
16-Mar-2017 ET |
2017 |
342 |
3 |
TGba |
WUR Negotiation and Acknowledgement Procedure Follow up |
Po-Kai Huang (Intel) |
16-Mar-2017 13:55:56 ET |
Download |
16-Mar-2017 ET |
2017 |
343 |
2 |
TGba |
WUR Beacon |
Po-Kai Huang (Intel) |
16-Mar-2017 03:08:03 ET |
Download |
16-Mar-2017 ET |
2017 |
342 |
2 |
TGba |
WUR Negotiation and Acknowledgement Procedure Follow up |
Po-Kai Huang (Intel) |
16-Mar-2017 03:07:23 ET |
Download |
15-Mar-2017 ET |
2017 |
271 |
4 |
TGax |
CR for 17.2.2.1 and 17.3.9.10 |
Po-Kai Huang (Intel) |
15-Mar-2017 18:05:26 ET |
Download |
15-Mar-2017 ET |
2017 |
271 |
3 |
TGax |
CR for 17.2.2.1 and 17.3.9.10 |
Po-Kai Huang (Intel) |
15-Mar-2017 16:48:00 ET |
Download |
14-Mar-2017 ET |
2017 |
342 |
1 |
TGba |
WUR Negotiation and Acknowledgement Procedure Follow up |
Po-Kai Huang (Intel) |
14-Mar-2017 14:36:22 ET |
Download |
14-Mar-2017 ET |
2017 |
343 |
1 |
TGba |
WUR Beacon |
Po-Kai Huang (Intel) |
14-Mar-2017 14:35:33 ET |
Download |
13-Mar-2017 ET |
2017 |
302 |
2 |
TGax |
CR for 27.5.2.4 |
Po-Kai Huang (Intel) |
13-Mar-2017 02:14:52 ET |
Download |
09-Mar-2017 ET |
2017 |
264 |
3 |
TGax |
CR for 10.3.2.8a |
Po-Kai Huang (Intel) |
09-Mar-2017 13:00:01 ET |
Download |
08-Mar-2017 ET |
2017 |
271 |
2 |
TGax |
CR for 17.2.2.1 and 17.3.9.10 |
Po-Kai Huang (Intel) |
08-Mar-2017 20:53:00 ET |
Download |
08-Mar-2017 ET |
2017 |
263 |
3 |
TGax |
CR for 27.11.5 |
Po-Kai Huang (Intel) |
08-Mar-2017 19:27:24 ET |
Download |
08-Mar-2017 ET |
2017 |
324 |
1 |
TGax |
CR for 10.3.2.4 and 27.2.2 Part I |
Po-Kai Huang (Intel) |
08-Mar-2017 19:22:46 ET |
Download |
08-Mar-2017 ET |
2017 |
264 |
2 |
TGax |
CR for 10.3.2.8a |
Po-Kai Huang (Intel) |
08-Mar-2017 16:02:06 ET |
Download |
07-Mar-2017 ET |
2017 |
343 |
0 |
TGba |
WUR Beacon |
Po-Kai Huang (Intel) |
13-Mar-2017 02:11:35 ET |
Download |
07-Mar-2017 ET |
2017 |
342 |
0 |
TGba |
WUR Negotiation and Acknowledgement Procedure Follow up |
Po-Kai Huang (Intel) |
13-Mar-2017 02:11:09 ET |
Download |
06-Mar-2017 ET |
2017 |
263 |
2 |
TGax |
CR for 27.11.5 |
Po-Kai Huang (Intel) |
06-Mar-2017 18:52:03 ET |
Download |
06-Mar-2017 ET |
2017 |
324 |
0 |
TGax |
CR for 10.3.2.4 and 27.2.2 Part I |
Po-Kai Huang (Intel) |
06-Mar-2017 18:56:15 ET |
Download |
06-Mar-2017 ET |
2017 |
263 |
1 |
TGax |
CR for 27.11.5 |
Po-Kai Huang (Intel) |
06-Mar-2017 14:52:50 ET |
Download |
02-Mar-2017 ET |
2017 |
302 |
1 |
TGax |
CR for 27.5.2.4 |
Po-Kai Huang (Intel) |
02-Mar-2017 18:47:15 ET |
Download |
02-Mar-2017 ET |
2017 |
271 |
1 |
TGax |
CR for 17.2.2.1 and 17.3.9.10 |
Po-Kai Huang (Intel) |
02-Mar-2017 13:06:08 ET |
Download |
27-Feb-2017 ET |
2017 |
302 |
0 |
TGax |
CR for 27.5.2.4 |
Po-Kai Huang (Intel) |
27-Feb-2017 19:46:20 ET |
Download |
23-Feb-2017 ET |
2017 |
207 |
6 |
TGax |
CR for 9.3.1.23.4 |
Po-Kai Huang (Intel) |
23-Feb-2017 11:44:56 ET |
Download |
19-Feb-2017 ET |
2017 |
271 |
0 |
TGax |
CR for 17.2.2.1 and 17.3.9.10 |
Po-Kai Huang (Intel) |
19-Feb-2017 23:45:22 ET |
Download |
19-Feb-2017 ET |
2017 |
264 |
1 |
TGax |
CR for 10.3.2.8a |
Po-Kai Huang (Intel) |
19-Feb-2017 23:20:27 ET |
Download |
16-Feb-2017 ET |
2017 |
207 |
5 |
TGax |
CR for 9.3.1.23.4 |
Po-Kai Huang (Intel) |
16-Feb-2017 13:52:50 ET |
Download |
15-Feb-2017 ET |
2017 |
207 |
4 |
TGax |
CR for 9.3.1.23.4 |
Po-Kai Huang (Intel) |
15-Feb-2017 12:21:52 ET |
Download |
15-Feb-2017 ET |
2017 |
264 |
0 |
TGax |
CR for 10.3.2.8a |
Po-Kai Huang (Intel) |
15-Feb-2017 12:20:08 ET |
Download |
15-Feb-2017 ET |
2017 |
263 |
0 |
TGax |
CR for 27.11.5 |
Po-Kai Huang (Intel) |
15-Feb-2017 12:16:39 ET |
Download |
02-Feb-2017 ET |
2017 |
207 |
3 |
TGax |
CR for 9.3.1.23.4 |
Po-Kai Huang (Intel) |
02-Feb-2017 13:07:07 ET |
Download |
02-Feb-2017 ET |
2017 |
207 |
2 |
TGax |
CR for 9.3.1.23.4 |
Po-Kai Huang (Intel) |
02-Feb-2017 12:34:54 ET |
Download |
01-Feb-2017 ET |
2017 |
207 |
1 |
TGax |
CR for 9.3.1.23.4 |
Po-Kai Huang (Intel) |
01-Feb-2017 19:26:33 ET |
Download |
31-Jan-2017 ET |
2017 |
207 |
0 |
TGax |
CR for 9.3.1.23.4 |
Po-Kai Huang (Intel) |
31-Jan-2017 18:02:36 ET |
Download |
16-Jan-2017 ET |
2017 |
85 |
1 |
TGax |
CR for 9.2.5.2 and 9.2.5.7 |
Po-Kai Huang (Intel) |
16-Jan-2017 17:12:30 ET |
Download |
16-Jan-2017 ET |
2017 |
85 |
0 |
TGax |
CR for 9.2.5.2 and 9.2.5.7 |
Po-Kai Huang (Intel) |
16-Jan-2017 10:38:30 ET |
Download |
15-Jan-2017 ET |
2017 |
71 |
0 |
TGba |
High Level MAC Concept for WUR |
Po-Kai Huang (Intel) |
18-Jan-2017 15:32:17 ET |
Download |
05-Nov-2016 ET |
2016 |
1390 |
0 |
TGax |
Spec Text: Revision for NAV Setting Rule under Immediate Response |
Po-Kai Huang (Intel) |
07-Nov-2016 01:16:10 ET |
Download |
05-Nov-2016 ET |
2016 |
1389 |
0 |
TGax |
Comment Resolution for CID 807 |
Po-Kai Huang (Intel) |
05-Nov-2016 13:28:05 ET |
Download |
05-Nov-2016 ET |
2016 |
1121 |
2 |
TGax |
Spec Texts: Spatial Reuse Indication for Trigger |
Po-Kai Huang (Intel) |
07-Nov-2016 01:16:35 ET |
Download |
20-Oct-2016 ET |
2016 |
1339 |
1 |
TGax |
Comment Resolution for Some Remaining NAV CIDs |
Po-Kai Huang (Intel) |
20-Oct-2016 11:39:45 ET |
Download |
18-Oct-2016 ET |
2016 |
1339 |
0 |
TGax |
Comment Resolution for Some Remaining NAV CIDs |
Po-Kai Huang (Intel) |
18-Oct-2016 17:35:03 ET |
Download |
13-Sep-2016 ET |
2016 |
1173 |
2 |
TGax |
Comment Resolution on Two NAVs - Part II |
Po-Kai Huang (Intel) |
13-Sep-2016 09:42:07 ET |
Download |
13-Sep-2016 ET |
2016 |
1173 |
1 |
TGax |
Comment Resolution on Two NAVs - Part II |
Po-Kai Huang (Intel) |
13-Sep-2016 09:00:57 ET |
Download |
12-Sep-2016 ET |
2016 |
1106 |
2 |
TGax |
Comment Resolution on Two NAVs - Part I |
Po-Kai Huang (Intel) |
12-Sep-2016 15:31:52 ET |
Download |
10-Sep-2016 ET |
2016 |
1173 |
0 |
TGax |
Comment Resolution on Two NAVs - Part II |
Po-Kai Huang (Intel) |
12-Sep-2016 04:15:03 ET |
Download |
02-Sep-2016 ET |
2016 |
1121 |
1 |
TGax |
Spec Texts: Spatial Reuse Indication for Trigger |
Po-Kai Huang (Intel) |
02-Sep-2016 18:19:00 ET |
Download |
29-Aug-2016 ET |
2016 |
1122 |
0 |
TGax |
Comment Resolution for CID 995, 2597, 2584 |
Po-Kai Huang (Intel) |
29-Aug-2016 22:21:48 ET |
Download |
29-Aug-2016 ET |
2016 |
1121 |
0 |
TGax |
Spec Texts: Spatial Reuse Indication for Trigger |
Po-Kai Huang (Intel) |
29-Aug-2016 22:12:32 ET |
Download |
24-Aug-2016 ET |
2016 |
1106 |
1 |
TGax |
Comment Resolution on Two NAVs - Part I |
Po-Kai Huang (Intel) |
24-Aug-2016 20:06:52 ET |
Download |
18-Aug-2016 ET |
2016 |
1106 |
0 |
TGax |
Comment Resolution on Two NAVs - Part I |
Po-Kai Huang (Intel) |
18-Aug-2016 19:58:22 ET |
Download |
15-Aug-2016 ET |
2016 |
886 |
3 |
TGax |
Comment Resolution for some UL MU CS TBD |
Po-Kai Huang (Intel) |
15-Aug-2016 12:55:21 ET |
Download |
11-Aug-2016 ET |
2016 |
885 |
3 |
TGax |
Comment Resolution on UL MU CS NAV Considerstion |
Po-Kai Huang (Intel) |
11-Aug-2016 11:20:39 ET |
Download |
11-Aug-2016 ET |
2016 |
887 |
1 |
TGax |
Spec Text for MU-RTS restriction on HE MU PPDU |
Po-Kai Huang (Intel) |
11-Aug-2016 11:11:00 ET |
Download |
11-Aug-2016 ET |
2016 |
885 |
2 |
TGax |
Comment Resolution on UL MU CS NAV Considerstion |
Po-Kai Huang (Intel) |
11-Aug-2016 00:11:30 ET |
Download |
10-Aug-2016 ET |
2016 |
886 |
2 |
TGax |
Comment Resolution for some UL MU CS TBD |
Po-Kai Huang (Intel) |
10-Aug-2016 23:58:15 ET |
Download |
09-Aug-2016 ET |
2016 |
890 |
2 |
TGax |
Comment Resolution on NAV Setting of Single and Multiple Protection and Control Response |
Po-Kai Huang (Intel) |
09-Aug-2016 12:57:52 ET |
Download |
26-Jul-2016 ET |
2016 |
808 |
2 |
TGax |
Comment Resolution on Trigger Frame Format - MU-RTS variant |
Po-Kai Huang (Intel) |
26-Jul-2016 12:45:52 ET |
Download |
26-Jul-2016 ET |
2016 |
807 |
2 |
TGax |
Comment Resolution on MU-RTS/CTS Procedure |
Po-Kai Huang (Intel) |
26-Jul-2016 12:44:55 ET |
Download |
25-Jul-2016 ET |
2016 |
886 |
1 |
TGax |
Comment Resolution for some UL MU CS TBD |
Po-Kai Huang (Intel) |
25-Jul-2016 21:03:16 ET |
Download |
25-Jul-2016 ET |
2016 |
885 |
1 |
TGax |
Comment Resolution on UL MU CS NAV Considerstion |
Po-Kai Huang (Intel) |
25-Jul-2016 20:55:35 ET |
Download |
25-Jul-2016 ET |
2016 |
890 |
1 |
TGax |
Comment Resolution on NAV Setting of Single and Multiple Protection and Control Response |
Po-Kai Huang (Intel) |
25-Jul-2016 20:39:20 ET |
Download |
25-Jul-2016 ET |
2016 |
951 |
0 |
TGax |
Setting for TXOP Duration Field |
Po-Kai Huang (Intel) |
25-Jul-2016 03:13:21 ET |
Download |
23-Jul-2016 ET |
2016 |
890 |
0 |
TGax |
Comment Resolution on NAV Setting of Single and Multiple Protection and Control Response |
Po-Kai Huang (Intel) |
25-Jul-2016 02:04:59 ET |
Download |
23-Jul-2016 ET |
2016 |
887 |
0 |
TGax |
Spec Text for MU-RTS restriction on HE MU PPDU |
Po-Kai Huang (Intel) |
25-Jul-2016 02:03:51 ET |
Download |
23-Jul-2016 ET |
2016 |
886 |
0 |
TGax |
Comment Resolution for some UL MU CS TBD |
Po-Kai Huang (Intel) |
25-Jul-2016 02:02:51 ET |
Download |
23-Jul-2016 ET |
2016 |
885 |
0 |
TGax |
Comment Resolution on UL MU CS NAV Considerstion |
Po-Kai Huang (Intel) |
25-Jul-2016 02:01:53 ET |
Download |
18-Jul-2016 ET |
2016 |
808 |
1 |
TGax |
Comment Resolution on Trigger Frame Format - MU-RTS variant |
Po-Kai Huang (Intel) |
18-Jul-2016 13:47:57 ET |
Download |
18-Jul-2016 ET |
2016 |
807 |
1 |
TGax |
Comment Resolution on MU-RTS/CTS Procedure |
Po-Kai Huang (Intel) |
18-Jul-2016 13:47:12 ET |
Download |
28-Jun-2016 ET |
2016 |
808 |
0 |
TGax |
Comment Resolution on Trigger Frame Format - MU-RTS variant |
Po-Kai Huang (Intel) |
28-Jun-2016 17:52:52 ET |
Download |
28-Jun-2016 ET |
2016 |
807 |
0 |
TGax |
Comment Resolution on MU-RTS/CTS Procedure |
Po-Kai Huang (Intel) |
28-Jun-2016 20:48:02 ET |
Download |
15-May-2016 ET |
2016 |
648 |
0 |
TGax |
MU-RTS/CTS PHY Format |
Po-Kai Huang (Intel) |
16-May-2016 12:06:52 ET |
Download |
15-May-2016 ET |
2016 |
647 |
0 |
TGax |
Consideration of Spatial Reuse for Trigger Frame |
Po-Kai Huang (Intel) |
16-May-2016 12:04:43 ET |
Download |
18-Jan-2016 ET |
2016 |
90 |
1 |
TGah |
SB0 Comment Resolution for CIDs 8095, 8108, 8123 |
Po-Kai Huang (Intel) |
18-Jan-2016 14:06:23 ET |
Download |
18-Jan-2016 ET |
2016 |
90 |
0 |
TGah |
SB0 Comment Resolution for CIDs 8095, 8108, 8123 |
Po-Kai Huang (Intel) |
18-Jan-2016 03:01:43 ET |
Download |
11-Nov-2015 ET |
2015 |
1326 |
2 |
TGax |
NAV Consideration for UL MU Response Follow Up |
Po-Kai Huang (Intel) |
11-Nov-2015 12:54:58 ET |
Download |