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27-Apr-2025 19:58:34 ET
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Created (ET) Year DCN Rev Group Title Author (Affiliation) Uploaded (ET) Actions
11-Oct-2021 ET
2021 1229 3 TGbe CR_PHY_TxBlocks Xiaogang Chen (Intel)
11-Oct-2021 20:12:51 ET
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27-Sep-2021 ET
2021 1229 2 TGbe CR_PHY_TxBlocks Xiaogang Chen (Intel)
27-Sep-2021 18:16:52 ET
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16-Sep-2021 ET
2021 1229 1 TGbe CR_PHY_TxBlocks Xiaogang Chen (Intel)
16-Sep-2021 09:29:02 ET
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22-Jul-2021 ET
2021 1229 0 TGbe CR_PHY_TxBlocks Xiaogang Chen (Intel)
06-Aug-2021 12:20:29 ET
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10-Apr-2025 ET
2025 585 1 TGbn CR-PHY-cc50-CIDs_in_subclause_38.3.25_Receiver_specification Juan Fang (Intel)
10-Apr-2025 11:43:02 ET
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02-Apr-2025 ET
2025 585 0 TGbn CR-PHY-cc50-CIDs_in_subclause_38.3.25_Receiver_specification Juan Fang (Intel)
08-Apr-2025 14:39:02 ET
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03-Apr-2025 ET
2025 584 1 TGbn CR-PHY-cc50-CIDs_in_subclause_38.3.19_Transmit_requirements_for_PPDUs_sent_in_response_to_a_triggering_frame Juan Fang (Intel)
03-Apr-2025 11:12:27 ET
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02-Apr-2025 ET
2025 584 0 TGbn CR-PHY-cc50-CIDs_in_subclause_38.3.19_Transmit_requirements_for_PPDUs_sent_in_response_to_a_triggering_frame Juan Fang (Intel)
02-Apr-2025 14:08:29 ET
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10-Apr-2025 ET
2025 623 1 TGbn CR-PHY-cc50-CIDs_in_subclause_38.3.15.2.1_Cyclic_shift_for_pre_UHR_modulated_fields_CID_1345_2443 Juan Fang (Intel)
10-Apr-2025 11:40:29 ET
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07-Apr-2025 ET
2025 623 0 TGbn CR-PHY-cc50-CIDs_in_subclause_38.3.15.2.1_Cyclic_shift_for_pre_UHR_modulated_fields_CID_1345_2443 Juan Fang (Intel)
07-Apr-2025 13:53:56 ET
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10-Apr-2025 ET
2025 608 2 TGbn CR-PHY-cc50-CIDs_in_subclause_38.3.15.12_ELR-SIG-part2 Juan Fang (Intel)
10-Apr-2025 11:38:49 ET
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07-Apr-2025 ET
2025 608 1 TGbn CR-PHY-cc50-CIDs_in_subclause_38.3.15.12_ELR-SIG-part2 Juan Fang (Intel)
07-Apr-2025 01:36:01 ET
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06-Apr-2025 ET
2025 608 0 TGbn CR-PHY-cc50-CIDs_in_subclause_38.3.15.12_ELR-SIG-part2 Juan Fang (Intel)
06-Apr-2025 20:26:19 ET
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03-Apr-2025 ET
2025 564 3 TGbn CR-PHY-cc50-CIDs_in_subclause_38.3.15.12_ELR-SIG_38.3.16.1_coding Juan Fang (Intel)
03-Apr-2025 11:04:34 ET
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02-Apr-2025 ET
2025 564 2 TGbn CR-PHY-cc50-CIDs_in_subclause_38.3.15.12_ELR-SIG_38.3.16.1_coding Juan Fang (Intel)
02-Apr-2025 17:16:06 ET
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02-Apr-2025 ET
2025 564 1 TGbn CR-PHY-cc50-CIDs_in_subclause_38.3.15.12_ELR-SIG_38.3.16.1_coding Juan Fang (Intel)
02-Apr-2025 13:22:35 ET
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31-Mar-2025 ET
2025 564 0 TGbn CR-PHY-cc50-CIDs_in_subclause_38.3.15.12_ELR-SIG_38.3.16.1_coding Juan Fang (Intel)
31-Mar-2025 17:57:15 ET
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04-Feb-2020 ET
2020 278 0 TGba CR on TGba D6.0 Po-Kai Huang (Intel)
04-Feb-2020 19:41:43 ET
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18-May-2016 ET
2016 653 5 TGax CR on section 26.3.3 Xiaogang Chen (Intel)
18-May-2016 23:56:45 ET
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18-May-2016 ET
2016 653 4 TGax CR on section 26.3.3 Xiaogang Chen (Intel)
18-May-2016 23:37:01 ET
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18-May-2016 ET
2016 653 3 TGax CR on section 26.3.3 Xiaogang Chen (Intel)
18-May-2016 23:28:02 ET
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18-May-2016 ET
2016 653 2 TGax CR on section 26.3.3 Xiaogang Chen (Intel)
18-May-2016 20:22:58 ET
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16-May-2016 ET
2016 653 1 TGax CR on section 26.3.3 Xiaogang Chen (Intel)
16-May-2016 14:53:59 ET
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15-May-2016 ET
2016 653 0 TGax CR on section 26.3.3 Xiaogang Chen (Intel)
16-May-2016 02:27:13 ET
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16-May-2019 ET
2019 932 1 TGba CR on remaining CIDs Po-Kai Huang (Intel)
16-May-2019 15:00:54 ET
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16-May-2019 ET
2019 932 0 TGba CR on remaining CIDs Po-Kai Huang (Intel)
16-May-2019 13:41:06 ET
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12-Jul-2017 ET
2017 985 4 TGax CR on NDP feedback PHY Xiaogang Chen (Intel)
12-Jul-2017 08:04:22 ET
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11-Jul-2017 ET
2017 985 3 TGax CR on NDP feedback PHY Xiaogang Chen (Intel)
11-Jul-2017 15:26:47 ET
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11-Jul-2017 ET
2017 985 2 TGax CR on NDP feedback PHY Xiaogang Chen (Intel)
11-Jul-2017 11:40:52 ET
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10-Jul-2017 ET
2017 985 1 TGax CR on NDP feedback PHY Xiaogang Chen (Intel)
10-Jul-2017 10:17:23 ET
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05-Jul-2017 ET
2017 985 0 TGax CR on NDP feedback PHY Xiaogang Chen (Intel)
10-Jul-2017 04:34:03 ET
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13-May-2019 ET
2019 670 1 TGay CR on MU BA and RD Ilya Bolotin (Intel)
13-May-2019 10:10:01 ET
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22-Apr-2019 ET
2019 670 0 TGay CR on MU BA and RD Ilya Bolotin (Intel)
11-May-2019 21:53:31 ET
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06-Jan-2022 ET
2021 1511 3 TGbe CR on MSCS/SCS clarifications Dibakar Das (Intel)
06-Jan-2022 11:59:12 ET
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06-Dec-2021 ET
2021 1511 2 TGbe CR on MSCS/SCS clarifications Dibakar Das (Intel)
06-Dec-2021 12:47:54 ET
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02-Dec-2021 ET
2021 1511 1 TGbe CR on MSCS/SCS clarifications Dibakar Das (Intel)
02-Dec-2021 09:50:05 ET
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13-Sep-2021 ET
2021 1511 0 TGbe CR on MSCS/SCS clarifications Dibakar Das (Intel)
14-Sep-2021 17:34:54 ET
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11-Jul-2017 ET
2017 986 2 TGax CR on Introduction Xiaogang Chen (Intel)
11-Jul-2017 06:21:00 ET
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10-Jul-2017 ET
2017 986 1 TGax CR on Introduction Xiaogang Chen (Intel)
10-Jul-2017 10:16:54 ET
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05-Jul-2017 ET
2017 986 0 TGax CR on Introduction Xiaogang Chen (Intel)
10-Jul-2017 04:34:44 ET
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14-Nov-2019 ET
2019 1684 5 TGax CR on dot11HECCAIndicationMode Robert Stacey (Intel)
14-Nov-2019 16:33:31 ET
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13-Nov-2019 ET
2019 1684 4 TGax CR on dot11HECCAIndicationMode Robert Stacey (Intel)
13-Nov-2019 17:58:39 ET
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12-Nov-2019 ET
2019 1684 3 TGax CR on dot11HECCAIndicationMode Robert Stacey (Intel)
12-Nov-2019 21:47:30 ET
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11-Nov-2019 ET
2019 1684 2 TGax CR on dot11HECCAIndicationMode Robert Stacey (Intel)
11-Nov-2019 13:56:59 ET
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18-Sep-2019 ET
2019 1684 1 TGax CR on dot11HECCAIndicationMode Robert Stacey (Intel)
18-Sep-2019 22:21:43 ET
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18-Sep-2019 ET
2019 1684 0 TGax CR on dot11HECCAIndicationMode Robert Stacey (Intel)
18-Sep-2019 19:44:58 ET
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10-Sep-2018 ET
2018 1519 1 TGax CR on control response Robert Stacey (Intel)
10-Sep-2018 12:40:40 ET
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05-Sep-2018 ET
2018 1519 0 TGax CR on control response Robert Stacey (Intel)
05-Sep-2018 20:33:59 ET
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07-May-2018 ET
2018 905 0 TGay CR on CIDs for Clause 10.61 Kerstin Johnsson (Intel)
21-Jun-2018 19:02:34 ET
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20-Jun-2024 ET
2024 919 4 TGbh CR on activated vs supported Robert Stacey (Intel)
20-Jun-2024 12:37:05 ET
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15-May-2024 ET
2024 919 3 TGbh CR on activated vs supported Robert Stacey (Intel)
15-May-2024 03:51:40 ET
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14-May-2024 ET
2024 919 2 TGbh CR on activated vs supported Robert Stacey (Intel)
14-May-2024 03:55:35 ET
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14-May-2024 ET
2024 919 1 TGbh CR on activated vs supported Robert Stacey (Intel)
14-May-2024 03:16:15 ET
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14-May-2024 ET
2024 919 0 TGbh CR on activated vs supported Robert Stacey (Intel)
14-May-2024 02:15:37 ET
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04-May-2018 ET
2018 767 2 TGax CR on 27.5.6 Misc laurent cariou (Intel)
04-May-2018 08:43:35 ET
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04-May-2018 ET
2018 767 1 TGax CR on 27.5.6 Misc laurent cariou (Intel)
04-May-2018 08:22:26 ET
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30-Apr-2018 ET
2018 767 0 TGax CR on 27.5.6 Misc laurent cariou (Intel)
02-May-2018 08:37:11 ET
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10-May-2018 ET
2018 768 5 TGax CR on 27.14.3 Misc laurent cariou (Intel)
10-May-2018 03:49:45 ET
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10-May-2018 ET
2018 768 4 TGax CR on 27.14.3 Misc laurent cariou (Intel)
10-May-2018 03:41:53 ET
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10-May-2018 ET
2018 768 3 TGax CR on 27.14.3 Misc laurent cariou (Intel)
10-May-2018 03:08:14 ET
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10-May-2018 ET
2018 768 2 TGax CR on 27.14.3 Misc laurent cariou (Intel)
10-May-2018 01:58:53 ET
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09-May-2018 ET
2018 768 1 TGax CR on 27.14.3 Misc laurent cariou (Intel)
09-May-2018 10:06:51 ET
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30-Apr-2018 ET
2018 768 0 TGax CR on 27.14.3 Misc laurent cariou (Intel)
02-May-2018 08:39:56 ET
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15-Sep-2016 ET
2016 1227 2 TGax cr-on-26-3-7 Shahrnaz Azizi (Intel Corporation)
15-Sep-2016 03:59:01 ET
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15-Sep-2016 ET
2016 1227 1 TGax cr-on-26-3-7 Shahrnaz Azizi (Intel Corporation)
15-Sep-2016 03:37:15 ET
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12-Sep-2016 ET
2016 1227 0 TGax cr-on-26-3-7 Shahrnaz Azizi (Intel Corporation)
12-Sep-2016 02:53:41 ET
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18-Jan-2018 ET
2017 1828 4 TGax CR MU EDCA parameters laurent cariou (Intel)
18-Jan-2018 14:36:08 ET
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17-Jan-2018 ET
2017 1828 3 TGax CR MU EDCA parameters laurent cariou (Intel)
17-Jan-2018 20:34:07 ET
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12-Jan-2018 ET
2017 1828 2 TGax CR MU EDCA parameters laurent cariou (Intel)
12-Jan-2018 14:52:25 ET
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11-Jan-2018 ET
2017 1828 1 TGax CR MU EDCA parameters laurent cariou (Intel)
11-Jan-2018 12:02:06 ET
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28-Nov-2017 ET
2017 1828 0 TGax CR MU EDCA parameters laurent cariou (Intel)
09-Jan-2018 19:15:26 ET
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18-Aug-2020 ET
2020 717 11 TGax CR_MISC_PHY Xiaogang Chen (Intel)
18-Aug-2020 17:15:30 ET
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13-Aug-2020 ET
2020 717 10 TGax CR_MISC_PHY Xiaogang Chen (Intel)
13-Aug-2020 10:41:41 ET
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04-Aug-2020 ET
2020 717 9 TGax CR_MISC_PHY Xiaogang Chen (Intel)
04-Aug-2020 17:36:02 ET
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30-Jul-2020 ET
2020 717 8 TGax CR_MISC_PHY Xiaogang Chen (Intel)
30-Jul-2020 18:05:08 ET
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28-May-2020 ET
2020 717 7 TGax CR_MISC_PHY Xiaogang Chen (Intel)
28-May-2020 21:58:21 ET
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28-May-2020 ET
2020 717 6 TGax CR_MISC_PHY Xiaogang Chen (Intel)
28-May-2020 18:35:01 ET
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26-May-2020 ET
2020 717 5 TGax CR_MISC_PHY Xiaogang Chen (Intel)
26-May-2020 10:48:00 ET
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21-May-2020 ET
2020 717 4 TGax CR_MISC_PHY Xiaogang Chen (Intel)
21-May-2020 17:16:49 ET
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21-May-2020 ET
2020 717 3 TGax CR_MISC_PHY Xiaogang Chen (Intel)
21-May-2020 01:48:30 ET
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14-May-2020 ET
2020 717 2 TGax CR_MISC_PHY Xiaogang Chen (Intel)
14-May-2020 17:17:22 ET
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14-May-2020 ET
2020 717 1 TGax CR_MISC_PHY Xiaogang Chen (Intel)
14-May-2020 13:02:28 ET
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07-May-2020 ET
2020 717 0 TGax CR_MISC_PHY Xiaogang Chen (Intel)
07-May-2020 20:05:43 ET
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17-Jan-2019 ET
2019 25 1 TGba CR Misc. Minyoung Park (Intel Corp.)
17-Jan-2019 01:25:48 ET
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07-Jan-2019 ET
2019 25 0 TGba CR Misc. Minyoung Park (Intel Corp.)
09-Jan-2019 14:00:17 ET
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16-Jan-2019 ET
2019 177 1 TGax CR Misc laurent cariou (Intel)
16-Jan-2019 16:31:08 ET
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16-Jan-2019 ET
2019 177 0 TGax CR Misc laurent cariou (Intel)
16-Jan-2019 00:29:25 ET
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27-May-2020 ET
2020 802 1 TGba CR for WUR Wake-up Operation Part I Po-Kai Huang (Intel)
27-May-2020 00:29:16 ET
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21-May-2020 ET
2020 802 0 TGba CR for WUR Wake-up Operation Part I Po-Kai Huang (Intel)
24-May-2020 10:47:45 ET
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31-Oct-2019 ET
2019 1794 1 TGba CR for WUR Wake-up Operation Po-Kai Huang (Intel)
31-Oct-2019 18:24:33 ET
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28-Oct-2019 ET
2019 1794 0 TGba CR for WUR Wake-up Operation Po-Kai Huang (Intel)
29-Oct-2019 16:12:01 ET
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07-Jan-2019 ET
2018 1966 4 TGba CR for WUR transmit procedure Vinod Kristem (Intel Corporation)
07-Jan-2019 23:23:01 ET
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15-Nov-2018 ET
2018 1966 3 TGba CR for WUR transmit procedure Vinod Kristem (Intel Corporation)
15-Nov-2018 10:36:45 ET
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13-Nov-2018 ET
2018 1966 2 TGba CR for WUR transmit procedure Vinod Kristem (Intel Corporation)
13-Nov-2018 02:38:41 ET
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13-Nov-2018 ET
2018 1966 1 TGba CR for WUR transmit procedure Vinod Kristem (Intel Corporation)
13-Nov-2018 01:43:33 ET
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11-Nov-2018 ET
2018 1966 0 TGba CR for WUR transmit procedure Vinod Kristem (Intel Corporation)
12-Nov-2018 18:54:36 ET
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08-Jan-2019 ET
2018 1965 6 TGba CR for WUR receive procedure Vinod Kristem (Intel Corporation)
08-Jan-2019 00:03:43 ET
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07-Jan-2019 ET
2018 1965 5 TGba CR for WUR receive procedure Vinod Kristem (Intel Corporation)
07-Jan-2019 23:24:46 ET
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15-Nov-2018 ET
2018 1965 4 TGba CR for WUR receive procedure Vinod Kristem (Intel Corporation)
15-Nov-2018 10:35:25 ET
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13-Nov-2018 ET
2018 1965 3 TGba CR for WUR receive procedure Vinod Kristem (Intel Corporation)
13-Nov-2018 03:19:54 ET
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