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30-Apr-2025 04:11:32 ET
Documents
Created (ET) Year DCN Rev Group Title Author (Affiliation) Uploaded (ET) Actions
25-Jul-2017 ET
2017 1182 0 TGay OFDM spoofing error length indicator Claudio da Silva (Intel)
11-Aug-2017 17:50:40 ET
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25-Jul-2017 ET
2017 1181 0 TGay Contributions to the BRP TXSS procedure Claudio da Silva (Intel)
31-Jul-2017 12:57:54 ET
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19-Jul-2017 ET
2017 1175 0 TGay Proposed resolution to BF PHY related CIDs Claudio da Silva (Intel)
24-Jul-2017 18:44:25 ET
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10-Jul-2017 ET
2017 1042 1 TGay CE TRN Transmission in BRP TXSS Claudio da Silva (Intel)
10-Jul-2017 04:34:29 ET
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09-Jul-2017 ET
2017 1042 0 TGay CE TRN Transmission in BRP TXSS Claudio da Silva (Intel)
10-Jul-2017 03:21:22 ET
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21-Jun-2017 ET
2017 924 0 TGay Data TRN transition interval Claudio da Silva (Intel)
03-Jul-2017 18:24:43 ET
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21-Jun-2017 ET
2017 923 0 TGay TRN Subfield Indexing Claudio da Silva (Intel)
03-Jul-2017 18:13:36 ET
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21-Jun-2017 ET
2017 919 1 TGay Resolution to 11ay related CIDs Claudio da Silva (Intel)
21-Jun-2017 12:39:04 ET
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20-Jun-2017 ET
2017 919 0 TGay Resolution to 11ay related CIDs Claudio da Silva (Intel)
20-Jun-2017 13:00:18 ET
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14-Mar-2017 ET
2017 323 2 TGay Draft text for BRP Transmit Sector Sweep Claudio da Silva (Intel)
14-Mar-2017 11:43:41 ET
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13-Mar-2017 ET
2017 322 1 TGay BRP Transmit Sector Sweep Claudio da Silva (Intel)
13-Mar-2017 20:47:45 ET
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13-Mar-2017 ET
2017 323 1 TGay Draft text for BRP Transmit Sector Sweep Claudio da Silva (Intel)
13-Mar-2017 20:27:01 ET
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06-Mar-2017 ET
2017 323 0 TGay Draft text for BRP Transmit Sector Sweep Claudio da Silva (Intel)
11-Mar-2017 12:11:38 ET
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06-Mar-2017 ET
2017 322 0 TGay BRP Transmit Sector Sweep Claudio da Silva (Intel)
11-Mar-2017 12:11:18 ET
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21-Feb-2017 ET
2017 278 0 TGay Maximum TRN field duration Claudio da Silva (Intel)
27-Feb-2017 12:50:29 ET
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21-Feb-2017 ET
2017 277 0 TGay EDMG Control Mode Data Field Claudio da Silva (Intel)
27-Feb-2017 12:52:26 ET
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24-Jan-2017 ET
2017 189 0 TGay Beam tracking request for EDMG SC mode Claudio da Silva (Intel)
12-Feb-2017 17:13:36 ET
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18-Jan-2017 ET
2017 149 2 TGay EDMG-CEF Extension for SC MIMO Claudio da Silva (Intel)
18-Jan-2017 08:39:13 ET
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17-Jan-2017 ET
2017 149 1 TGay EDMG-CEF Extension for SC MIMO Claudio da Silva (Intel)
17-Jan-2017 20:40:51 ET
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17-Jan-2017 ET
2017 149 0 TGay EDMG-CEF Extension for SC MIMO Claudio da Silva (Intel)
17-Jan-2017 15:31:10 ET
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16-Jan-2017 ET
2017 7 1 TGay Training Field Structure Definition Claudio da Silva (Intel)
16-Jan-2017 13:54:46 ET
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16-Jan-2017 ET
2017 52 1 TGay Header-A Definition for EDMG Control Mode Claudio da Silva (Intel)
16-Jan-2017 11:16:47 ET
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14-Jan-2017 ET
2017 53 0 TGay Spoofing of EDMG Control Mode PPDUs Claudio da Silva (Intel)
15-Jan-2017 21:12:59 ET
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14-Jan-2017 ET
2017 52 0 TGay Header-A Definition for EDMG Control Mode Claudio da Silva (Intel)
15-Jan-2017 17:30:35 ET
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06-Jan-2017 ET
2017 7 0 TGay Training Field Structure Definition Claudio da Silva (Intel)
15-Jan-2017 17:01:56 ET
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21-Dec-2016 ET
2016 1631 0 TGay 6 9 2 Beam refinement Claudio da Silva (Intel)
21-Dec-2016 14:06:41 ET
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21-Dec-2016 ET
2016 1630 0 TGay 6 4 EDMG control mode Claudio da Silva (Intel)
21-Dec-2016 14:05:41 ET
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07-Nov-2016 ET
2016 1364 1 TGay TRN field transmission for channel bonding Claudio da Silva (Intel)
07-Nov-2016 11:11:20 ET
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15-Nov-2018 ET
2018 1949 4 TGaz Annex B PICS Chitto Ghosh (Intel corporation)
15-Nov-2018 00:15:26 ET
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14-Nov-2018 ET
2018 1949 3 TGaz Annex B PICS Chitto Ghosh (Intel corporation)
14-Nov-2018 22:50:20 ET
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14-Nov-2018 ET
2018 1949 2 TGaz Annex B PICS Chitto Ghosh (Intel corporation)
14-Nov-2018 02:43:35 ET
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11-Nov-2018 ET
2018 1949 1 TGaz Annex B PICS Chitto Ghosh (Intel corporation)
11-Nov-2018 20:59:44 ET
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11-Nov-2018 ET
2018 1949 0 TGaz Annex B PICS Chitto Ghosh (Intel corporation)
11-Nov-2018 06:47:35 ET
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16-Sep-2020 ET
2020 1104 4 TGm Proposed Changes in SCs 10.23.2.2 and 10.23.2.9 Chittabrata Ghosh (Intel Corporation)
16-Sep-2020 15:47:40 ET
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15-Sep-2020 ET
2020 1104 3 TGm Proposed Changes in SCs 10.23.2.2 and 10.23.2.9 Chittabrata Ghosh (Intel Corporation)
15-Sep-2020 17:38:59 ET
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10-Sep-2020 ET
2020 1104 2 TGm Proposed Changes in SCs 10.23.2.2 and 10.23.2.9 Chittabrata Ghosh (Intel Corporation)
10-Sep-2020 22:12:52 ET
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16-Jul-2020 ET
2020 1104 1 TGm Proposed Changes in SCs 10.23.2.2 and 10.23.2.9 Chittabrata Ghosh (Intel Corporation)
16-Jul-2020 21:33:08 ET
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16-Jul-2020 ET
2020 1104 0 TGm Proposed Changes in SCs 10.23.2.2 and 10.23.2.9 Chittabrata Ghosh (Intel Corporation)
16-Jul-2020 14:56:26 ET
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23-Jun-2020 ET
2020 884 4 TGax Resolution for CIDs related to UORA Chittabrata Ghosh (Intel Corporation)
23-Jun-2020 17:29:15 ET
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23-Jun-2020 ET
2020 884 3 TGax Resolution for CIDs related to UORA Chittabrata Ghosh (Intel Corporation)
23-Jun-2020 14:17:49 ET
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11-Jun-2020 ET
2020 884 2 TGax Resolution for CIDs related to UORA Chittabrata Ghosh (Intel Corporation)
11-Jun-2020 21:09:04 ET
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11-Jun-2020 ET
2020 884 1 TGax Resolution for CIDs related to UORA Chittabrata Ghosh (Intel Corporation)
11-Jun-2020 19:04:01 ET
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10-Jun-2020 ET
2020 884 0 TGax Resolution for CIDs related to UORA Chittabrata Ghosh (Intel Corporation)
10-Jun-2020 12:05:54 ET
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18-Sep-2019 ET
2019 1682 0 TGax Comment resolution for UORA Chittabrata Ghosh (Intel Corporation)
18-Sep-2019 21:53:29 ET
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17-Mar-2016 ET
2016 482 0 LRLP TIG March 2016 Minutes Chittabrata Ghosh (Intel Corporation)
17-Mar-2016 03:54:35 ET
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17-Feb-2016 ET
2015 1446 8 LRLP TIG LRLP Output Report Draft Chittabrata Ghosh (Intel Corporation)
17-Feb-2016 12:08:15 ET
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17-Feb-2016 ET
2015 1446 7 LRLP TIG LRLP Output Report Draft Chittabrata Ghosh (Intel Corporation)
17-Feb-2016 10:54:18 ET
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22-Jan-2016 ET
2015 1446 6 LRLP TIG LRLP Output Report Draft Chittabrata Ghosh (Intel Corporation)
22-Jan-2016 08:08:19 ET
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21-Jan-2016 ET
2015 1446 5 LRLP TIG LRLP Output Report Draft Chittabrata Ghosh (Intel Corporation)
21-Jan-2016 12:07:53 ET
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07-Mar-2018 ET
2018 534 1 TGaz Draft Text on Trigger Frame format for 11az Chittabrata Ghosh (Intel)
07-Mar-2018 13:10:57 ET
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05-Mar-2018 ET
2018 534 0 TGaz Draft Text on Trigger Frame format for 11az Chittabrata Ghosh (Intel)
07-Mar-2018 10:33:36 ET
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16-Jan-2018 ET
2018 229 0 TGaz Sequence Authentication Code (SAC) Signaling in SU and MU Ranging Chittabrata Ghosh (Intel)
18-Jan-2018 12:14:05 ET
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07-Nov-2017 ET
2017 1770 0 TGaz Protected LTF Using PMF in SU and MU Modes Chittabrata Ghosh (Intel)
08-Nov-2017 08:11:27 ET
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06-Nov-2017 ET
2017 1739 0 TGaz Power Save Operation for Ranging Measurements Chittabrata Ghosh (Intel)
08-Nov-2017 00:16:23 ET
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12-Sep-2017 ET
2017 1455 1 TGaz MU Measurement and Feedback Scheduling Chittabrata Ghosh (Intel)
12-Sep-2017 18:04:19 ET
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11-Sep-2017 ET
2017 1455 0 TGaz MU Measurement and Feedback Scheduling Chittabrata Ghosh (Intel)
12-Sep-2017 14:41:02 ET
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13-Jul-2017 ET
2017 688 4 TGax LB225 11ax D1.0 Comment Resolution 27.10.4 - Part II Chittabrata Ghosh (Intel)
13-Jul-2017 03:18:47 ET
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13-Jul-2017 ET
2017 688 3 TGax LB225 11ax D1.0 Comment Resolution 27.10.4 - Part II Chittabrata Ghosh (Intel)
13-Jul-2017 02:20:58 ET
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11-Jul-2017 ET
2017 1128 0 TGaz Target Wake Time for Measurement Scheduling Chittabrata Ghosh (Intel)
13-Jul-2017 06:22:54 ET
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11-Jul-2017 ET
2017 1126 0 TGaz MU Negotiation for Unassociated STAs - Follow Up Chittabrata Ghosh (Intel)
11-Jul-2017 09:04:39 ET
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09-Jul-2017 ET
2017 1036 0 WNG SC WLAN-IOT: Low Complexity & Constrained Peak Power Consumption WLAN Chittabrata Ghosh (Intel)
10-Jul-2017 13:51:20 ET
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15-Jun-2017 ET
2017 688 2 TGax LB225 11ax D1.0 Comment Resolution 27.10.4 - Part II Chittabrata Ghosh (Intel)
15-Jun-2017 18:45:06 ET
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24-May-2017 ET
2017 688 1 TGax LB225 11ax D1.0 Comment Resolution 27.10.4 - Part II Chittabrata Ghosh (Intel)
24-May-2017 21:11:02 ET
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09-May-2017 ET
2017 802 1 TGaz MU Ranging for Unassociated STAs Chittabrata Ghosh (Intel)
09-May-2017 08:09:56 ET
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09-May-2017 ET
2017 801 1 TGaz Discussion on FTM Frame Protection Chittabrata Ghosh (Intel)
09-May-2017 02:28:58 ET
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09-May-2017 ET
2017 758 1 TGaz Trigger Frame Format for 11az Chittabrata Ghosh (Intel)
09-May-2017 02:26:20 ET
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09-May-2017 ET
2017 598 2 TGaz Polling for MU measurements Chittabrata Ghosh (Intel)
09-May-2017 02:22:19 ET
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08-May-2017 ET
2017 802 0 TGaz MU Ranging for Unassociated STAs Chittabrata Ghosh (Intel)
09-May-2017 00:41:34 ET
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08-May-2017 ET
2017 801 0 TGaz Discussion on FTM Frame Protection Chittabrata Ghosh (Intel)
08-May-2017 23:02:30 ET
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07-May-2017 ET
2017 758 0 TGaz Trigger Frame Format for 11az Chittabrata Ghosh (Intel)
08-May-2017 22:49:27 ET
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02-May-2017 ET
2017 688 0 TGax LB225 11ax D1.0 Comment Resolution 27.10.4 - Part II Chittabrata Ghosh (Intel)
02-May-2017 21:56:13 ET
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19-Apr-2017 ET
2017 598 1 TGaz Polling for MU measurements Chittabrata Ghosh (Intel)
19-Apr-2017 09:56:54 ET
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14-Apr-2017 ET
2017 598 0 TGaz Polling for MU measurements Chittabrata Ghosh (Intel)
19-Apr-2017 02:52:40 ET
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18-Jan-2017 ET
2017 120 2 TGaz Secured Location Threat Model Chittabrata Ghosh (Intel)
18-Jan-2017 14:19:55 ET
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18-Jan-2017 ET
2017 120 1 TGaz Secured Location Threat Model Chittabrata Ghosh (Intel)
18-Jan-2017 13:41:08 ET
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16-Jan-2017 ET
2017 120 0 TGaz Secured Location Threat Model Chittabrata Ghosh (Intel)
16-Jan-2017 11:53:44 ET
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07-Nov-2016 ET
2016 1496 0 TGaz 11ax-based MU Negotiation Phase Chittabrata Ghosh (Intel)
08-Nov-2016 09:33:10 ET
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07-Nov-2016 ET
2016 1458 0 TGax Comment Resolution for Sub-clause 25.13.2 Chittabrata Ghosh (Intel)
07-Nov-2016 00:41:07 ET
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14-Sep-2016 ET
2016 1222 1 TGax Comment Resolution on UL OFDMA Random Access Chittabrata Ghosh (Intel)
14-Sep-2016 11:40:12 ET
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13-Sep-2016 ET
2016 1260 0 TGaz Location Measurement Protocol for Unassociated STAs Chittabrata Ghosh (Intel)
13-Sep-2016 05:40:03 ET
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12-Sep-2016 ET
2016 1224 0 TGax Random Access Paramer Set (RAPS) element Chittabrata Ghosh (Intel)
12-Sep-2016 01:36:54 ET
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11-Sep-2016 ET
2016 1222 0 TGax Comment Resolution on UL OFDMA Random Access Chittabrata Ghosh (Intel)
12-Sep-2016 01:33:36 ET
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27-Jul-2016 ET
2016 1033 0 LRLP TIG Minutes from May meeting Chittabrata Ghosh (Intel)
27-Jul-2016 17:50:48 ET
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26-Jul-2016 ET
2016 1015 0 TGaz Location Measurement Protocol for 11ax Chittabrata Ghosh (Intel)
26-Jul-2016 15:04:46 ET
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24-Jul-2016 ET
2016 938 0 TGax Comment Resolution for Sub-clause 25.10.4 Chittabrata Ghosh (Intel)
25-Jul-2016 02:12:51 ET
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16-May-2016 ET
2016 667 0 TGax Signaling of Multi-TID Aggregation Limit Chittabrata Ghosh (Intel)
16-May-2016 13:21:54 ET
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15-Mar-2016 ET
2016 363 1 LRLP TIG Discussion on LRLP Timeline Chittabrata Ghosh (Intel)
15-Mar-2016 23:21:38 ET
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15-Mar-2016 ET
2016 362 1 TGax Multi-TID Aggregation Limit Chittabrata Ghosh (Intel)
15-Mar-2016 00:21:18 ET
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13-Mar-2016 ET
2016 363 0 LRLP TIG Discussion on LRLP Timeline Chittabrata Ghosh (Intel)
13-Mar-2016 23:18:32 ET
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13-Mar-2016 ET
2016 362 0 TGax Multi-TID Aggregation Limit Chittabrata Ghosh (Intel)
13-Mar-2016 23:31:42 ET
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22-Jan-2016 ET
2016 199 0 LRLP TIG January 2016 meeting minutes Chittabrata Ghosh (Intel)
22-Jan-2016 10:46:45 ET
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08-Nov-2015 ET
2015 1365 0 LRLP TIG Use Cases of LRLP Operation for IoTs Chittabrata Ghosh (Intel)
11-Nov-2015 00:39:26 ET
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08-Nov-2015 ET
2015 1364 0 TGax Signaling Trigger Information for STAs in 11ax Chittabrata Ghosh (Intel)
09-Nov-2015 08:09:43 ET
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17-Sep-2015 ET
2015 1194 0 LRLP TIG LRLP session minutes Chittabrata Ghosh (Intel)
02-Nov-2015 14:50:39 ET
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15-Sep-2015 ET
2015 1100 2 TGax Discussion on Deep and Shallow Sleep States Chittabrata Ghosh (Intel)
15-Sep-2015 05:34:24 ET
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14-Sep-2015 ET
2015 1112 1 LRLP TIG Use Case of LRLP Operation for IoT Chittabrata Ghosh (Intel)
14-Sep-2015 04:07:22 ET
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13-Sep-2015 ET
2015 1100 1 TGax Discussion on Deep and Shallow Sleep States Chittabrata Ghosh (Intel)
13-Sep-2015 20:37:32 ET
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13-Sep-2015 ET
2015 1112 0 LRLP TIG Use Case of LRLP Operation for IoT Chittabrata Ghosh (Intel)
13-Sep-2015 20:32:19 ET
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13-Sep-2015 ET
2015 1108 0 LRLP TIG Technical Feasibility for LRLP Chittabrata Ghosh (Intel)
13-Sep-2015 20:29:18 ET
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13-Sep-2015 ET
2015 1107 0 TGax Power Save with Random Access Chittabrata Ghosh (Intel)
13-Sep-2015 20:42:29 ET
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