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Created (ET) Year DCN Rev Group Title Author (Affiliation) Uploaded (ET) Actions
07-Nov-2015 ET
2015 1325 0 TGax MU-RTS/CTS Follow Up Po-Kai Huang (Intel)
09-Nov-2015 00:14:43 ET
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22-Sep-2015 ET
2015 132 9 TGax Spec Framework Robert Stacey (Intel)
22-Sep-2015 17:50:26 ET
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18-Sep-2015 ET
2015 132 8 TGax Spec Framework Robert Stacey (Intel)
18-Sep-2015 18:14:34 ET
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16-Sep-2015 ET
2015 1143 3 TGax tgax Sept 2015 Spatial Reuse ad-hoc meeting agenda laurent cariou (Intel)
16-Sep-2015 04:13:21 ET
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16-Sep-2015 ET
2015 1143 2 TGax tgax Sept 2015 Spatial Reuse ad-hoc meeting agenda laurent cariou (Intel)
16-Sep-2015 00:36:56 ET
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15-Sep-2015 ET
2015 1143 1 TGax tgax Sept 2015 Spatial Reuse ad-hoc meeting agenda laurent cariou (Intel)
15-Sep-2015 08:30:59 ET
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15-Sep-2015 ET
2015 1100 2 TGax Discussion on Deep and Shallow Sleep States Chittabrata Ghosh (Intel)
15-Sep-2015 05:34:24 ET
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15-Sep-2015 ET
2015 602 6 TGax HE-LTF squence for UL MU-MIMO Xiaogang Chen (Intel)
15-Sep-2015 01:06:15 ET
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14-Sep-2015 ET
2015 1062 1 TGax NAV Consideration for UL MU Response to Trigger frame Po-Kai Huang (Intel)
14-Sep-2015 23:36:03 ET
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14-Sep-2015 ET
2015 1149 0 TGax Updated Simulation Results for Box5 Calibration Intel Corp.
14-Sep-2015 03:18:44 ET
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14-Sep-2015 ET
2015 1143 0 TGax tgax Sept 2015 Spatial Reuse ad-hoc meeting agenda laurent cariou (Intel)
15-Sep-2015 02:28:42 ET
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13-Sep-2015 ET
2015 602 5 TGax HE-LTF squence for UL MU-MIMO Xiaogang Chen (Intel)
13-Sep-2015 21:17:03 ET
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13-Sep-2015 ET
2015 1100 1 TGax Discussion on Deep and Shallow Sleep States Chittabrata Ghosh (Intel)
13-Sep-2015 20:37:32 ET
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13-Sep-2015 ET
2015 1107 0 TGax Power Save with Random Access Chittabrata Ghosh (Intel)
13-Sep-2015 20:42:29 ET
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13-Sep-2015 ET
2015 1105 0 TGax UL OFDMA-based Random Access Procedure Chittabrata Ghosh (Intel)
13-Sep-2015 20:41:43 ET
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13-Sep-2015 ET
2015 1103 0 TGax DL Sounding Sequence with UL MU Feedback Chittabrata Ghosh (Intel)
13-Sep-2015 20:40:21 ET
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13-Sep-2015 ET
2015 1102 0 TGax Fragmentation with MU Operation Chittabrata Ghosh (Intel)
13-Sep-2015 20:39:08 ET
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13-Sep-2015 ET
2015 1100 0 TGax Discussion on Deep and Shallow Sleep States Chittabrata Ghosh (Intel)
13-Sep-2015 11:45:42 ET
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12-Sep-2015 ET
2015 1062 0 TGax NAV Consideration for UL MU Response to Trigger frame Po-Kai Huang (Intel)
13-Sep-2015 19:57:24 ET
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20-Jul-2015 ET
2015 132 7 TGax Spec Framework Robert Stacey (Intel)
20-Jul-2015 17:36:54 ET
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16-Jul-2015 ET
2015 833 3 TGax Calibration results for PSP and UAPSD for 20, 40 and 80MHz bands Dmitry Akhmetov (Intel)
16-Jul-2015 16:42:15 ET
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14-Jul-2015 ET
2015 867 1 TGax MU-RTS/CTS for DL MU Po-Kai Huang (Intel)
14-Jul-2015 19:06:17 ET
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14-Jul-2015 ET
2015 875 1 TGax Random Access with Trigger Frames using OFDMA Chittabrata Ghosh (Intel)
14-Jul-2015 14:19:16 ET
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13-Jul-2015 ET
2015 833 2 TGax Calibration results for PSP and UAPSD for 20, 40 and 80MHz bands Dmitry Akhmetov (Intel)
13-Jul-2015 15:05:29 ET
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13-Jul-2015 ET
2015 833 1 TGax Calibration results for PSP and UAPSD for 20, 40 and 80MHz bands Dmitry Akhmetov (Intel)
13-Jul-2015 14:47:14 ET
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13-Jul-2015 ET
2015 849 3 TGax Simulation Results for Box5 Calibration Rongzhen Yang (Intel)
13-Jul-2015 14:30:59 ET
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13-Jul-2015 ET
2015 875 0 TGax Random Access with Trigger Frames using OFDMA Chittabrata Ghosh (Intel)
13-Jul-2015 04:58:56 ET
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13-Jul-2015 ET
2015 849 2 TGax Simulation Results for Box5 Calibration Rongzhen Yang (Intel)
13-Jul-2015 04:31:16 ET
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13-Jul-2015 ET
2015 867 0 TGax MU-RTS/CTS for DL MU Po-Kai Huang (Intel)
13-Jul-2015 05:11:29 ET
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13-Jul-2015 ET
2015 849 1 TGax Simulation Results for Box5 Calibration Rongzhen Yang (Intel)
13-Jul-2015 03:12:20 ET
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13-Jul-2015 ET
2015 602 4 TGax HE-LTF squence for UL MU-MIMO Qinghua Li (Intel)
13-Jul-2015 03:11:59 ET
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12-Jul-2015 ET
2015 849 0 TGax Simulation Results for Box5 Calibration Rongzhen Yang (Intel)
12-Jul-2015 23:27:11 ET
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12-Jul-2015 ET
2015 833 0 TGax Calibration results for PSP and UAPSD for 20, 40 and 80MHz bands Dmitry Akhmetov (Intel)
12-Jul-2015 05:01:46 ET
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09-Jul-2015 ET
2015 132 6 TGax Spec Framework Robert Stacey (Intel)
09-Jul-2015 21:33:00 ET
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26-May-2015 ET
2015 662 1 TGax tgax may 2015 vancouver Spatial Reuse ad-hoc meeting minutes laurent cariou (Intel)
26-May-2015 12:06:40 ET
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14-May-2015 ET
2015 132 5 TGax Spec Framework Robert Stacey (Intel)
14-May-2015 18:22:03 ET
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14-May-2015 ET
2015 330 5 TGax OFDMA Numerology and Structure Shahrnaz Azizi (Intel Corporation)
14-May-2015 16:43:53 ET
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14-May-2015 ET
2015 576 2 TGax Latency and Power Consumption in State Transitions Chittabrata Ghosh (Intel)
14-May-2015 11:21:37 ET
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13-May-2015 ET
2015 602 3 TGax HE-LTF squence for UL MU-MIMO Qinghua Li (Intel)
13-May-2015 18:16:52 ET
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13-May-2015 ET
2015 330 4 TGax OFDMA Numerology and Structure Shahrnaz Azizi (Intel Corporation)
13-May-2015 11:57:52 ET
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12-May-2015 ET
2015 662 0 TGax tgax may 2015 vancouver Spatial Reuse ad-hoc meeting minutes laurent cariou (Intel)
12-May-2015 23:26:11 ET
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11-May-2015 ET
2015 604 1 TGax Random Access with Trigger Frames using OFDMA Chittabrata Ghosh (Intel)
11-May-2015 18:02:30 ET
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11-May-2015 ET
2015 602 2 TGax HE-LTF squence for UL MU-MIMO Qinghua Li (Intel)
11-May-2015 17:57:12 ET
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11-May-2015 ET
2015 576 1 TGax Latency and Power Consumption in State Transitions Chittabrata Ghosh (Intel)
11-May-2015 14:40:41 ET
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11-May-2015 ET
2015 602 1 TGax HE-LTF squence for UL MU-MIMO Qinghua Li (Intel)
11-May-2015 13:24:53 ET
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11-May-2015 ET
2015 330 3 TGax OFDMA Numerology and Structure Shahrnaz Azizi (Intel Corporation)
11-May-2015 10:24:31 ET
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11-May-2015 ET
2015 604 0 TGax Random Access with Trigger Frames using OFDMA Chittabrata Ghosh (Intel)
11-May-2015 10:34:41 ET
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11-May-2015 ET
2015 603 0 TGax Calibration Results for PSP and U-APSD Chittabrata Ghosh (Intel)
11-May-2015 00:59:15 ET
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11-May-2015 ET
2015 602 0 TGax HE-LTF squence for UL MU-MIMO Qinghua Li (Intel)
11-May-2015 00:30:21 ET
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10-May-2015 ET
2015 330 2 TGax OFDMA Numerology and Structure Shahrnaz Azizi (Intel Corporation)
10-May-2015 03:38:16 ET
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10-May-2015 ET
2015 576 0 TGax Latency and Power Consumption in State Transitions Chittabrata Ghosh (Intel)
11-May-2015 01:03:49 ET
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27-Mar-2015 ET
2015 132 4 TGax Spec Framework Robert Stacey (Intel)
27-Mar-2015 17:28:25 ET
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27-Mar-2015 ET
2015 132 3 TGax Spec Framework Robert Stacey (Intel)
27-Mar-2015 16:43:15 ET
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10-Mar-2015 ET
2015 314 2 TGax Sleep States in IEEE 802.11ax Simulation Scenarios Chittabrata Ghosh (Intel)
10-Mar-2015 03:22:33 ET
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09-Mar-2015 ET
2015 314 1 TGax Sleep States in IEEE 802.11ax Simulation Scenarios Chittabrata Ghosh (Intel)
09-Mar-2015 06:58:54 ET
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09-Mar-2015 ET
2015 330 1 TGax OFDMA Numerology and Structure Shahrnaz Azizi (Intel Corporation)
09-Mar-2015 06:31:20 ET
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06-Mar-2015 ET
2015 330 0 TGax OFDMA Numerology and Structure Shahrnaz Azizi (Intel Corporation)
08-Mar-2015 19:32:11 ET
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05-Mar-2015 ET
2015 314 0 TGax Sleep States in IEEE 802.11ax Simulation Scenarios Chittabrata Ghosh (Intel)
08-Mar-2015 19:17:11 ET
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15-Jan-2015 ET
2015 132 2 TGax Spec Framework Robert Stacey (Intel)
15-Jan-2015 15:50:10 ET
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14-Jan-2015 ET
2015 132 1 TGax Spec Framework Robert Stacey (Intel)
14-Jan-2015 08:55:33 ET
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13-Jan-2015 ET
2015 132 0 TGax Spec Framework Robert Stacey (Intel)
13-Jan-2015 10:32:43 ET
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05-Nov-2014 ET
2014 1453 2 TGax Spec Framework Proposal Robert Stacey (Intel)
05-Nov-2014 17:32:05 ET
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03-Nov-2014 ET
2014 1420 1 TGax The Impact of Preamble Error on MAC System Performance Po-Kai Huang (Intel)
03-Nov-2014 17:15:40 ET
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03-Nov-2014 ET
2014 1453 1 TGax Spec Framework Proposal Robert Stacey (Intel)
03-Nov-2014 10:22:18 ET
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03-Nov-2014 ET
2014 1453 0 TGax Spec Framework Proposal Robert Stacey (Intel)
03-Nov-2014 09:06:27 ET
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02-Nov-2014 ET
2014 1420 0 TGax The Impact of Preamble Error on MAC System Performance Po-Kai Huang (Intel)
03-Nov-2014 01:37:17 ET
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15-Sep-2014 ET
2014 1187 1 TGax The Effect of Preamble Error Model on MAC Simulator Po-Kai Huang (Intel)
15-Sep-2014 10:18:22 ET
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13-Sep-2014 ET
2014 1187 0 TGax The Effect of Preamble Error Model on MAC Simulator Po-Kai Huang (Intel)
14-Sep-2014 20:05:16 ET
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11-Jul-2014 ET
2014 832 0 TGax Performance Evaluation of OBSS Densification Po-Kai Huang (Intel)
14-Jul-2014 18:49:27 ET
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21-Dec-2020 ET
2020 1978 1 TGay Comments on TGay D7.0 Carlos Cordeiro (Intel)
21-Dec-2020 14:23:02 ET
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21-Dec-2020 ET
2020 1978 0 TGay Comments on TGay D7.0 Carlos Cordeiro (Intel)
21-Dec-2020 12:22:08 ET
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18-Nov-2020 ET
2020 1558 5 TGay Comments on TGay D6.0 Carlos Cordeiro (Intel)
18-Nov-2020 20:48:08 ET
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17-Nov-2020 ET
2020 1558 4 TGay Comments on TGay D6.0 Carlos Cordeiro (Intel)
17-Nov-2020 13:22:40 ET
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02-Nov-2020 ET
2020 1756 0 TGay Editorial Changes to 28.9.2.2.5 (TRN field definition) Claudio da Silva (Intel)
02-Nov-2020 08:58:18 ET
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26-Oct-2020 ET
2020 1558 3 TGay Comments on TGay D6.0 Carlos Cordeiro (Intel)
26-Oct-2020 22:25:11 ET
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26-Oct-2020 ET
2020 112 8 TGay SB000 comments on TGay D5.0 Carlos Cordeiro (Intel)
26-Oct-2020 21:22:27 ET
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26-Oct-2020 ET
2020 1558 2 TGay Comments on TGay D6.0 Carlos Cordeiro (Intel)
26-Oct-2020 21:21:41 ET
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01-Oct-2020 ET
2020 1558 1 TGay Comments on TGay D6.0 Carlos Cordeiro (Intel)
01-Oct-2020 13:00:29 ET
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30-Sep-2020 ET
2020 1558 0 TGay Comments on TGay D6.0 Carlos Cordeiro (Intel)
30-Sep-2020 16:14:28 ET
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13-Sep-2020 ET
2020 112 7 TGay SB000 comments on TGay D5.0 Carlos Cordeiro (Intel)
13-Sep-2020 21:07:57 ET
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12-Aug-2020 ET
2020 112 6 TGay SB000 comments on TGay D5.0 Carlos Cordeiro (Intel)
12-Aug-2020 10:37:53 ET
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12-Aug-2020 ET
2020 112 5 TGay SB000 comments on TGay D5.0 Carlos Cordeiro (Intel)
12-Aug-2020 10:33:26 ET
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22-Jul-2020 ET
2020 112 4 TGay SB000 comments on TGay D5.0 Carlos Cordeiro (Intel)
22-Jul-2020 21:12:43 ET
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09-May-2020 ET
2020 112 3 TGay SB000 comments on TGay D5.0 Carlos Cordeiro (Intel)
09-May-2020 14:53:45 ET
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22-Apr-2020 ET
2020 620 2 TGay Resolutions to CID 6228, 6229, 6230 Cheng Chen (Intel)
22-Apr-2020 10:22:19 ET
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22-Apr-2020 ET
2020 620 1 TGay Resolutions to CID 6228, 6229, 6230 Cheng Chen (Intel)
22-Apr-2020 01:06:00 ET
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15-Apr-2020 ET
2020 620 0 TGay Resolutions to CID 6228, 6229, 6230 Cheng Chen (Intel)
16-Apr-2020 16:19:32 ET
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01-Apr-2020 ET
2020 544 2 TGay Resolutions to SA ballot CIDs Cheng Chen (Intel)
01-Apr-2020 10:40:30 ET
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01-Apr-2020 ET
2020 544 1 TGay Resolutions to SA ballot CIDs Cheng Chen (Intel)
01-Apr-2020 01:24:00 ET
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25-Mar-2020 ET
2020 544 0 TGay Resolutions to SA ballot CIDs Cheng Chen (Intel)
30-Mar-2020 14:11:23 ET
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17-Mar-2020 ET
2020 112 2 TGay SB000 comments on TGay D5.0 Carlos Cordeiro (Intel)
17-Mar-2020 22:12:12 ET
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13-Feb-2020 ET
2020 327 1 TGay Initial SA Ballot Comment Resolution Claudio da Silva (Intel)
13-Feb-2020 14:02:45 ET
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11-Feb-2020 ET
2020 327 0 TGay Initial SA Ballot Comment Resolution Claudio da Silva (Intel)
12-Feb-2020 09:57:16 ET
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14-Jan-2020 ET
2020 112 1 TGay SB000 comments on TGay D5.0 Carlos Cordeiro (Intel)
14-Jan-2020 11:43:05 ET
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10-Jan-2020 ET
2020 112 0 TGay SB000 comments on TGay D5.0 Carlos Cordeiro (Intel)
10-Jan-2020 21:06:11 ET
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12-Nov-2019 ET
2019 1964 1 TGay Comments on TGay D5.0 Carlos Cordeiro (Intel)
12-Nov-2019 16:11:11 ET
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09-Nov-2019 ET
2019 1964 0 TGay Comments on TGay D5.0 Carlos Cordeiro (Intel)
09-Nov-2019 13:13:55 ET
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17-Sep-2019 ET
2019 1180 5 TGay Comments on TGay D4.0 Carlos Cordeiro (Intel)
17-Sep-2019 21:18:01 ET
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18-Jul-2019 ET
2019 1180 4 TGay Comments on TGay D4.0 Carlos Cordeiro (Intel)
18-Jul-2019 04:46:57 ET
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16-Jul-2019 ET
2019 1180 3 TGay Comments on TGay D4.0 Carlos Cordeiro (Intel)
16-Jul-2019 06:20:50 ET
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